This invention relates to the field of semiconductor integrated circuits and manufacturing, and more specifically to electrostatic discharges (ESD) protection in integrated circuits.
An overview of the field of ESD protection in integrated circuits appears in Amerasekera et al, ESD in Silicon Integrated Circuits (John Wiley andSons Ltd, 1995) and C. Duvvury et al. xe2x80x9cESD: A Pervasive Reliability Concern for IC Technologiesxe2x80x9d, Proceedings of the IEEE. Vol.81, No.5, May 1993, p.690-702.
ESD phenomena in silicon integrated circuits are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields, all factors that contribute to an increased sensitivity to damaging ESD events.
Dual voltage chip architectures are being introduced to offer the flexibility to maintain a higher operating voltage for peripheral input/output circuits while independently optimizing the core transistors. This increases the complexity of ESD protection circuits.
The challenge of cost reduction in this environment of increasing device complexity implies a drive for the use of a minimum number of process steps, a minimum number of photomasks and the application of standardized process conditions to the largest extend possible. There is a problem to improve conventional ESD protection circuits without introducing additional process steps or new process conditions, such as the use of additional ion implant conditions or implant species.
One of the commonly used components in an ESD protection circuit is an NMOS transistor which operates in the mode of a lateral bipolar npn transistor during an ESD event and provides a low impedance current path to ground. FIG. 1 depicts schematically the cross-section of such a lateral npn transistor. An epitaxial p-type silicon layer 2 has been grown on an p-type silicon substrate 1 and a p-well 3 has been formed by localized acceptor ion implantation and annealing. The n-plus collector region 4 and emitter region 5 were formed by shallow ion implants of donors. The surface between the emitter 5 and the collector 4 is covered by a gate oxide layer 6. Layers 7, 8, 9 and 10 provide metallic contacts to the gate, emitter, collector and the wafer backside, respectively.
To explain the present invention, the operation of the lateral npn transistor will first be described with the help of FIG. 2. The emitter, the gate and the wafer backside are connected to ground. A positive voltage spike at the collector, as caused by an ESD event, applies a reverse bias to the collector/base junction (the base is the epitaxial layer plus substrate). When the electric field in the depletion region exceeds the breakdown field, avalanching occurs. The avalanche mechanism forms electron/hole pairs. Electrons flow into the collector and holes flow into the p-type base. This hole current flows from the collector junction through the substrate to the backside contact, generating a positive, i.e. forward, bias, for the emitter/base junction. This emitter forward bias is proportional to the sum of the resistance components in the current path, which are schematically shown as R-PWELL and R-SUB in FIG.2. Those of the electrons injected from the emitter into the base which reach the collector depletion layer will participate in the avalanche mechanism. The electron concentration will be multiplied in accordance with the electric field dependent avalanche multiplication factor M. The resulting reduction of the device impedance is reflected in a xe2x80x9csnap backxe2x80x9d in the current-voltage characteristics of the device. As shown in FIG. 3, xe2x80x9csnap backxe2x80x9d, which corresponds to a xe2x80x9cturn onxe2x80x9d of the bipolar transistor, occurs at the collector voltage Vt1 with an associated collector current It1. The field dependence of the avalanche multiplication factor is responsible for the establishment of a new stable current/voltage equilibrium. At high electron injection levels base conductivity modulation also contributes towards making the device impedance positive again. It should be mentioned that the lateral npn transistor also protects against negative ESD pulses. Referring to FIG. 1, the collector 4 now acts as emitter and diverts the ESD current to the backside substrate contact 10 and to the now reverse biased emitter 5, which now acts as collector.
The current carrying capability of the device is limited by thermal effects in the avalanching collector depletion layer. A number of effects contribute to the onset of second (thermal) breakdown, such as the increase of intrinsic carrier concentration, ni, a reduced carrier mobility, a decrease in thermal conductivity, and a lowering of the potential barrier for tunnel currents. The second breakdown trigger current, shown as It2 in FIG. 3, is very sensitive to the device design, i.e. doping profiles, and is often used as a process monitor. The second breakdown results in junction melting and in an irreversible increase in leakage currents. It must be avoided for normal device operation.
For different ESD applications, the breakdown voltage of this device has to be adjusted. U.S. Pat. No. 5,539,233 described the application of specific ion implantation steps to control the doping profiles of the collector and base regions, thereby selecting the breakdown voltage of the device.
This invention provides methods to improve the high current capability of an NMOS transistor operating in a lateral npn bipolar transistor mode during an ESD event: the second breakdown trigger current is raised by adjusting the resistivity of the material between the avalanching collector/base pn-junction and the substrate contact on the backside of the silicon chip. Local ion implant steps are applied to achieve the improvements. Two preferred embodiments apply implant steps from a standard process flow and do not require an increase of the total number of process steps. The principle of the invention is also applicable to SCR-type ESD protection circuits.